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Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products Lead RTL development and integration Drive design reviews and quality standards Support verification and implementation teams MSc or
Technical leader responsible for HF analog layout strategy for broadband optical communication ICs or comparable RF ICs Lead layout architecture and floorplanning activities Develop and enforce layout methodologies Drive parasitic-aware implementations Support design teams through sign-off Mentor
