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Asic Developer Jobs In Lazio - 1 Job Positions Available

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Design Verification Engineer - VLSI/ASIC/FPGA

Altro ( Lazio LAZ )

Design Verification Engineer - VLSI/ASIC/FPGA Hardware Experience: 3 - 25 Years Location: Permanent Remote anywhere in the World Contract Length: 6 Months Type: Full time contract (8 hrs/day) Overlap Hours: 4 hrs/day with PST Mandatory Skills: Overall

Full-time AI VHDL Information Technology Ml Verilog 90,000 USD

Altro 13 days ago

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