NXP Semiconductors is looking for an outstanding contributor to join their Analog Layout team in Catania, Italy. This position involves delivering floorplan activities, participating in power supply strategies, and performing physical verifications for high-performance microcontrollers.The ideal
We are looking for a Physical Design Engineer to join our Analog Backend team and work on the digital island implementation within our analog chips. This role is ideal for someone who enjoys solving complex physical
A leading semiconductor solution provider is seeking a Physical Design Engineer to join the Analog Backend team in Catania, Italy. This role involves solving complex physical design challenges within analog chip environments and requires expertise in
I am recruiting for an Analog Layout Engineer on behalf of my client, a reputable organisation developing advanced IC solutions. This Analog Layout Engineer role offers a predominantly remote working arrangement and exposure to a range
Physical ASIC Design Implementation Engineer What you will do For more than 25 years, imec has been offering anASIC prototyping and production service to worldwide companies. Imec helps itscustomers to design their integrated circuits (chips) and
Your Profile : \*Working knowledge on advance tech nodes 16ff and below is highly desirable. \* Expert-level proficiency with industry-standard EDA tools from Synopsys (Fusion Compiler, ICC2, Primetime, Design Compiler), Cadence (Innovus, Tempus, Genus), or Siemens
Senior Silicon Physical Design Engineer – Axelera AI We are looking for a Senior Silicon Physical Design Engineer to develop cutting‑edge multi‑core in‑memory compute SoCs. The role covers the entire ASIC physical design flow from RTL
Be part of a fast-paced, start-up environment Job ID: 392341 Parm Shergill Analog | Mixed Signal | RFIC Design - EU I am recruiting for a Lead IC Layout Engineer to join my client’s team in
Experteer OverviewIn this role you shape analog layout for Marvell’s central engineering hub, delivering high-quality designs across multiple nodes. You’ll work with global teams to simulate, verify, and refine layouts using Cadence Virtuoso, shaping cutting‑edge technologies
Experteer OverviewIn dieser Rolle arbeiten Sie im Analog Backend Team an der digitalen Implementierung innerhalb unserer Analog-Chips. Sie lösen komplexe physikalische Design-Herausforderungen in Mixed-Signal-Umgebungen. Sie verantworten Floorplanning, Placement, CTS, Routing und Sign-off und optimieren Leistung, Zuverlässigkeit und
Experteer OverviewIn this role you will contribute to the development of Marvell’s next-generation high-speed PAM/Coherent DSPs and PHYs within a dynamic digital design team. You will define subsystem architecture and micro-architecture, develop RTL and integrate IPs,
We are looking for a Physical Design Engineer to join our Analog Backend team and work on the digital island implementation within our analog chips. This role is ideal for someone who enjoys solving complex physical
Experteer Overview In dieser Rolle arbeiten Sie im Analog Backend Team an der digitalen Implementierung innerhalb unserer Analog-Chips. Sie lösen komplexe physikalische Design-Herausforderungen in Mixed-Signal-Umgebungen. Sie verantworten Floorplanning, Placement, CTS, Routing und Sign-off und optimieren Leistung, Zuverlässigkeit
Senior Engineer - Silicon Physical Design (Italy based) Apply for the Senior Engineer - Silicon Physical Design (Italy based) role at Axelera AI . About Us Axelera AI is not your regular deep-tech startup. We are
Renesas is looking for a Physical Design Engineer to join their Analog Backend team in Catania, Italy. This role focuses on the implementation of ASIC physical design flow, including tasks such as floorplanning, placement optimization, and routing.
Experteer Italy in Catania sucht einen erfahrenen ASIC Physical Designer, der für die Optimierung von Designs und die Durchführung von Power-Integrity-Analysen verantwortlich ist. In dieser Position arbeiten Sie eng mit globalen Teams und tragen zur digitalen
IC Resources is seeking an Analog Layout Engineer to develop advanced IC solutions with a predominantly remote working arrangement. This role involves delivering custom analog and mixed signal IC layouts while collaborating closely with design teams.
Experteer OverviewIn this role you implement physical design for Optical Network ASICs across cutting‑edge nodes, learning new nodes and refining flows to achieve best‑in‑class power, performance, and area. You will work within cross‑functional hardware teams to
Experteer OverviewIn this role you will contribute to the development of high-speed PAM/Coherent DSPs and PHYs by crafting efficient RTL and integrating IPs. You’ll collaborate with architecture, verification, and back-end teams to ensure robust, clocked digital
Experteer OverviewIn this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize