NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore
NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore
Senior Engineer - Silicon Physical Design (Italy based) Apply for the Senior Engineer - Silicon Physical Design (Italy based) role at Axelera AI . About Us Axelera AI is not your regular deep-tech startup. We are
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Senior Silicon Physical Design Engineer – Axelera AI We are looking for a Senior Silicon Physical Design Engineer to develop cutting‑edge multi‑core in‑memory compute SoCs. The role covers the entire ASIC physical design flow from RTL
NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore
About Us Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years,
Experteer Overview In this role you will lead the digital IC design flow for SOCs within NXP’s Industrial & IoT Edge initiatives, partnering with analog, mixed‑signal, and software teams. You drive innovative architectures and verification strategies
Senior Engineer - Silicon Physical Design (Italy based) Apply for the Senior Engineer - Silicon Physical Design (Italy based) role at Axelera AI . About Us Axelera AI is not your regular deep-tech startup. We are
Senior Silicon Physical Design Engineer – Axelera AI We are looking for a Senior Silicon Physical Design Engineer to develop cutting‑edge multi‑core in‑memory compute So Cs. The role covers the entire ASIC physical design flow from
Your Profile : \*Working knowledge on advance tech nodes 16ff and below is highly desirable. \* Expert-level proficiency with industry-standard EDA tools from Synopsys (Fusion Compiler, ICC2, Primetime, Design Compiler), Cadence (Innovus, Tempus, Genus), or Siemens (APR,
Experteer Overview In this role you will lead the digital IC design flow for SOCs within NXP’s Industrial & IoT Edge initiatives, partnering with analog, mixed‑signal, and software teams. You drive innovative architectures and verification strategies