THE INTERNSHIP We are looking for an Intern to join our Automation team, which manages Siemens PCS7 DCS systems based on a virtualized infrastructure supporting production plants. During the internship, you will work alongside senior technicians
THE INTERNSHIP We are looking for an Intern to join our Automation team, which manages Siemens PCS7 DCS systems based on a virtualized infrastructure supporting production plants. During the internship, you will work alongside senior technicians
We are seeking a Principal Engineer – GaN Package Development to develop and industrialize advanced packaging technologies for GaN power devices and modules. You will drive package architecture, ensure performance, reliability, and cost targets, and lead cross‑functional
Select how often (in days) to receive an alert: Posting Date: 23 Mar 2026 City: Genova Location: Genova, IT, 16129 Catania, IT, 95131 Contract Type: Permanent Division: Civil Engineering Level of experience: Senior RINA is currently
We are seeking a Principal Engineer – GaN Package Development to develop and industrialize advanced packaging technologies for GaN power devices and modules. You will drive package architecture, ensure performance, reliability, and cost targets, and lead cross‑functional
WHO WE AREEtinars is a values-focused company with multi-year experience, specialised in the recruitment of professionals for niche markets, managing the full life-cycle of specialist and executive-level hires.At Etinars, we genuinely care about who you are
aizoOn , società di tecnologia e consulenza, indipendente, operante a livello globale, ricerca un / a Electronics Production Engineer - MES Integration. La risorsa sarà inserita nell’area Engineering della divisione Aerospace, Defense & Naval di aizoOn e
Overview We are looking for an Intern to join our Automation team, which manages Siemens PCS7 DCS systems based on a virtualized infrastructure supporting production plants. During the internship, you will work alongside senior technicians and
NXP in Catania is seeking a lead for the Analog Layout team to drive the full digital IC design flow for high-performance SOCs. You will shepherd RTL coding, synthesis, verification, and DFT while coordinating with analog,