Join NXP as a Senior AMS Verification leaderAt NXP, we create technologies that make the connected world better, safer, and more secure. Within the Advanced Power System team, we are looking for a Senior AMS Verification Engineer to
#WeAreIn for jobs that impact everyones life. Join the thinkers, builders, and problem-solvers behind tomorrow’s technology. As a Senior Staff Engineer Verification (f/m/div) in our Research & Development team, youll have the opportunity to merge creativity with
Digital Verification EngineerLocation: Milan, Italy – NXP SemiconductorsWe are looking for a motivated Digital Verification Engineer to join our R&D team in Milan. The successful candidate will contribute to the verification of complex mixed-signal ICs targeting automotive and industrial
The ams OSRAM Group is seeking a technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products. Based in Lombardy, Italy, you will contribute to advanced IC design
ams OSRAM is seeking a Technical Leader to own architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products. You will define digital subsystem architectures and lead RTL integration, while driving design reviews
Akronos Technologies Group, leader internazionale nei servizi di innovazione, ricerca e sviluppo e ingegneria ad alta tecnologia, punta ad ampliare il proprio team nel settore TELCO con il seguente profilo: Industria: Telecomunicazioni Profilo professionale: SoC/ASIC Design
#WeAreIn for jobs that impact everyones life. Build the future nobody’s dreamed of yet. are you ready to rethink the impossible? As a Principal Digital Design Engineer in our Research & Development team, youll have the
Requisition ID 24014 -Posted 08/13/2026 The ams OSRAM Group is a global leader in innovative light and sensor solutions. With more than 110 years of industry experience, we combine engineering excellence and global manufacturing with a
Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products Lead RTL development and integration Drive design reviews and quality standards Support verification and implementation teams MSc or PhD in