ResponsibilitiesLead and execute the full digital IC design flow for complex System‑on‑Chip (SOC), including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), formal verification, and power analysis.Contribute to design for testability (DFT)
OverviewExperteer OverviewAs Delivery Manager - Synthetics at GCAP HQ, you own the end-to-end delivery and evolution of the Synthetics Product Line, including Virtual Platform, Synthetic Environment, and Simulation Framework. You drive cross-domain integration, validation, and certification support,
# Engineer Research & Development SimulationApplylocations: Torino, ITtime type: Full timeposted on: Posted Todayjob requisition id: JR-14460 We are seeking great talent to help us build The DNA of tech. Vishay manufactures one of the worlds
Renesas is seeking a Senior Analog IC Design Engineer for our Power Product Group, Performance Computing Power Team in Catania (Italy). Reporting to the Director of Engineering, you will have responsibility for the design, verification and
Reporting to the Director of Design Engineering you will have responsibility for the design, verification and validation of power management IC’s. Your responsibilities encompass the full design cycle which spans product definition through IC validation. Responsibilities Perform transistor-level
Job SummaryWe are seeking an experienced Senior DFT Designer to contribute to the development of cutting‑edge mixed‑signal and digital integrated circuits. This role involves responsibility for designing, implementing, and verifying DFT architectures for complex SoCs working
Job Summary We are seeking an experienced Senior DFT Designer to contribute to the development of cutting-edge mixed-signal and digital integrated circuits. This role involves responsibility for designing, implementing, and verifying DFT architectures for complex SoCs
Experteer OverviewIn this role, you lead the Analog Layout team focused on high-performance MCU-oriented ICs. You will drive cross-functional digital IC design activities for complex SOCs, ensuring timing, power, and area targets are met. You will
Experteer OverviewDelivery Manager for GCAP HQ in Reading leads the end‑to‑end Requirements Engineering capabilities, driving a safe transition from legacy RM tools to a coherent target platform. You provide governance, data quality and cross‑partner integration to
Experteer OverviewIn this role you lead the Analog Layout team within NXP’s high-performance MCU and analog product initiatives. You will drive digital IC design flow for complex SOCs, collaborating with analog, mixed-signal, and software teams to