The Role: As a Physical Design Manager Engineer, you will serve as the technical reference point for the most complex digital blocks (high-speed, mixed-signal control, or automotive low-power). You will operate at the intersection of logic
Job Description We are looking for a Physical Design Engineer to join our Analog Backend team and work on the digital island implementation within our analog chips. This role is ideal for someone who enjoys solving
The Role: As a Physical Design Senior Engineer, you will take technical ownership of the implementation for highly complex digital blocks, including high-speed interfaces, mixed-signal control logic, and automotive low-power modules. Working at the intersection of
Renesas Electronics Corporation in Sicily, Italy, is seeking a seasoned Layout Design Engineer to work on DC‑DC converters, Controllers and Drivers. You will drive analog layout from block level to full chip, with a strong focus
Renesas Electronics is seeking an experienced Layout Design Engineer to work on DC-DC converters, controllers, and drivers. The role involves independent floorplanning and layout of analog circuits, taking ownership to meet the schedule and delivering high-quality layouts.
NXP is hiring a SoC Physical Design Leader in Catania to drive the physical design flow for high-performance MCU/SOC designs. The role requires deep expertise in floorplanning, timing, power integrity, STA, and DRC/LVS, with strong leadership and
Be part of a fast-paced, start-up environment Job ID: 392341 Parm Shergill Analog | Mixed Signal | RFIC Design - EU I am recruiting for a Lead IC Layout Engineer to join my client’s team in
Experteer Overview In this role you help digitally and analog‑front NAND design by delivering advanced layout blocks and driving intelligent, scalable layout approaches. You will work across analog, mixed‑signal and custom digital circuits, collaborating with multi‑functional
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Overview As a Layout Design Engineer, you will contribute to analog layout across DC-DC converters, controllers and drivers. You will own floorplanning and layout for analog blocks, driving design innovation and reliability. You’ll collaborate with global layout
Experteer Italy is seeking a Layout Design Engineer to own analog floorplanning for DC-DC converters, controllers and drivers, and to collaborate with global layout teams to deliver manufacturable layouts with tight schedules. You will drive EM and
NXP Italy in Catania is seeking an early‑career Analog Layout engineer to contribute to cutting‑edge MCU/ASIC projects. You will work on IP level floorplanning, analog blocks, and layout verification in a fast-paced environment. The role requires a
The Role As a Physical Design Manager Engineer, you will serve as the technical reference point for the most complex digital blocks (high‑speed, mixed‑signal control, or automotive low‑power). You will operate at the intersection of logic
Experteer Overview In this role you will contribute to the development of Marvell’s next-generation high-speed PAM/Coherent DSPs and PHYs within a dynamic digital design team. You will define subsystem architecture and micro-architecture, develop RTL and integrate
Experteer Overview In this role you shape analog layout for Marvell’s central engineering hub, delivering high-quality designs across multiple nodes. You’ll work with global teams to simulate, verify, and refine layouts using Cadence Virtuoso, shaping cutting‑edge
Experteer Overview In dieser Rolle arbeiten Sie im Analog Backend Team an der digitalen Implementierung innerhalb unserer Analog-Chips. Sie lösen komplexe physikalische Design-Herausforderungen in Mixed-Signal-Umgebungen. Sie verantworten Floorplanning, Placement, CTS, Routing und Sign-off und optimieren Leistung, Zuverlässigkeit
Experteer Italy is seeking an experienced engineer to shape analog layout for Marvell’s central engineering hub in Lombardia. This role involves delivering high-quality designs and collaborating with global teams using Cadence Virtuoso, managing development stages from
Your Profile : \*Working knowledge on advance tech nodes 16ff and below is highly desirable. \* Expert-level proficiency with industry-standard EDA tools from Synopsys (Fusion Compiler, ICC2, Primetime, Design Compiler), Cadence (Innovus, Tempus, Genus), or Siemens
I am recruiting for a Lead IC Layout Engineer to join my client’s team in Northern Italy, working on high performance semiconductor products. The Lead IC Layout Engineer will combine technical leadership with hands on delivery
Renesas is looking for a Physical Design Engineer to join their Analog Backend team in Catania, Italy. This role focuses on the implementation of ASIC physical design flow, including tasks such as floorplanning, placement optimization, and routing.